The present invention generally relates to producing at least one semiconductor entity on a substrate, wherein the semiconductor entity may have a generally rectangular or a cylindrical geometric shape.
Typically, “on-substrate” entities are formed, and sometimes treated, for inclusion at least partially in chips intended for electronics applications. Such applications include, for example, components for micro-electro-mechanical systems (MEMS), components for optics, or for optoelectronics such as light emitting diodes (LEDs) or laser diodes (LDs), or for optical receivers. The entities or chips are normally produced on a substrate in hundreds or thousands of units, normally arranged in a regular matrix.
After the chips are produced, they then have to be individualized or customized and then transferred to substrates termed “receivers”. The chip customization operation is often difficult to complete because it must be conducted in a particularly accurate and clean manner, in particular when the chips are intended for use in certain applications such as laser applications.
Semiconductor lasers emit light via mirrors, wherein the mirrors are positioned in the transverse facets of the chips wherein customization operations have taken place. Thus, chip customization must be carefully conducted to ensure good quality facets, so that flatness of the facets is maintained. There are several known chip customization techniques.
FIG. 1 shows a first known customization technique which utilizes a mechanical separation or cleavage process between the chips. In particular, FIG. 1a shows a series of cleavage starters such as a starter nick 11, produced in the appropriate crystallographic directions on the front face of the chips (not shown) using a tool with a hard point (such as a diamond tip). FIG. 1b shows a mechanical stress F exerted on the rear face of a substrate 10 at the starter nick 11 and in the direction of an appropriate crystallographic plane. This mechanical stress cleaves the substrate 10 along the starter nick 11 to create a plurality of strips each comprising a plurality of chips. FIG. 1c shows a diamond tip being used to split each strip 60 into a plurality of dies 61, 62, and 63, wherein each die includes at least one chip, thus customizing the chips. However, this first technique has a fairly low yield for large numbers of chips. Further, use of the first technique runs the risk of creating mechanical defects in the chips when applying the mechanical stress operation.
FIG. 2 illustrates a second known customization technique that utilizes chemical treatments between the chips. A mask 70 covers each chip 80 and protects that chip 80 from chemical attack, for example, from a simple dry etching process or from electromagnetic exposure during photolithography. The surrounding substrate is thus etched to form grooves between the chips. Final cutting is then carried out by conventional means to separate the dies.
The second technique described above appears to be more suitable than the first technique for fabricating large numbers of chips because it provides the possibility of simultaneously customizing all of the chips over the entire substrate surface. However, despite the protection conferred by the mask 70, the second technique does not protect from under etching at positions 81a, 81b, 81c, 81d, wherein a chemical attack takes place into the chip 80 beneath the mask 70. The second technique also causes unwanted etching 88 at the corners of the chip 80. This results in a reduced quality chip 80, in particular with regard to the flatness of its facets.
A third prior art customization technique is shown in FIG. 3. It comprises using reactive ion etching (RIE), which consists of etching the substrate 10 between the chips 80 in an isotropic manner. The substrate surface 10 is bombarded with natural ions 1000 having an energy suitable to etch the substrate 10 to thus customize the chips 80. However, this third technique often is expensive and difficult to conduct. Further, ion back-scattering 1001 can occur and these ions may etch the facets of the chip 80 resulting in a degraded, less planar chip.